Thermal modeling and temperature prediction in 3D ICs are important for improving performance and reliability. A number of numerical and analytical models have been developed for thermal analysis of 3D ICs. However, there is a relative lack of experimental work to determine key physical parameters in 3D IC thermal design. One such important key parameter is the inter-die thermal resistance between adjacent die bonded together. This paper describes a novel experimental method to measure the value of inter-die thermal resistance between two die in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the inter-die thermal resistance between two die is determined. There is good agreement between experimental measurement and theoretically estimated value of the inter-die thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

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