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Proceedings Papers

Power Envelope Analysis for the Thermal Optimization of a Chiplet Module

Eric Ouyang, Xiao Gu, Yonghyuk Jeong, Michael Liu
Proc. ASME. InterPACK2022, ASME 2022 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, V001T07A001, October 25–27, 2022
Publisher: American Society of Mechanical Engineers
Paper No: IPACK2022-97204
https://doi.org/10.1115/IPACK2022-97204
... the junction temperatures of dies using different power magnitudes. With the change of power magnitudes of the dies, a thermal resistor matrix was calculated. Finally, with the calculation of the thermal resistor matrix, a unique power envelope plot was developed to determine if the power magnitudes...
View Paper titled, <span class="search-highlight">Power</span> <span class="search-highlight">Envelope</span> Analysis for the Thermal Optimization of a Chiplet Module
Open the PDF for <span class="search-highlight">Power</span> <span class="search-highlight">Envelope</span> Analysis for the Thermal Optimization of a Chiplet Module in another window
Topics: Design, Heat sinks, Junctions, Optimization, Reliability, Resistors, Risk, Simulation, Temperature