This research concerns itself with a stress and reliability analysis of electronic packages with ultra-thin chips based on the finite element method. The effect of chip and substrate thickness, substrate material, presence of underfill, dimensions, and shape of the bump on stress reduction is analyzed. Obtained results clearly show that chip thinning, when used with an appropriate design of the entire package, can significantly decrease stresses and stress intensity factors and improve the reliability of the package. The developed software provides an effective design tool to quantify the reliability, stresses, and deflections of a package with ultra-thin chips.
1.
Francis
, D.
, 1999
, “Thinning Wafers for Flip Chip Applications
,” The Magazine of High-Density Interconnect
, 2
(5
), pp. 22
–25
.2.
Gradin
, P.
, 1982
, “A Fracture Criterion for Edge-Bonded Bimaterial Bodies
,” J. Compos. Mater.
, 16
, pp. 448
–456
.3.
Savruk
, M. P.
, Shkarayev
, S.
, and Madenci
, E.
, 1999
, “Stress Near Apex of Dissimilar Materials with Bilinear Behavior
,” J. Theoretical and Applied Fracture Mechanics
, 31
, pp. 203
–212
.4.
Gifford, N., and Hilton, P., 1981, “Preliminary Documentation of PAPST—Nonlinear Fracture and Stress Analysis by Finite Elements,” David W. Taylor Naval Ship Center.
5.
Chen, K., Zenner, R., Arneson, M., and Mountain, D., 1999, “Ultra-Thin Electronic Device Package,” 49th Electronic Components and Technology Conference, IEEE, San Diego, CA, pp. 657–662.
6.
Johnson, Z., 1999, “Implementation of and Extensions to Darveaux’s Approach to Finite Element Simulation of BGA Solder Joint Reliability,” 49th Electronic Components and Technology Conference, IEEE, San Diego, CA, pp. 1190–1195.
7.
Madenci
, E.
, Shkarayev
, S.
, and Mahajan
, R.
, 1998
, “Potential Failure Sites in a Flip-Chip Package With and Without Underfill
,” ASME J. Electron. Packag.
, 120
, pp. 336
–341
.Copyright © 2003
by ASME
You do not currently have access to this content.
